35.7.8 QSPI Interrupt Mask Register

The following configuration values are valid for all listed bit names of this register:

0: The corresponding interrupt is not enabled.

1: The corresponding interrupt is enabled.

Name: QSPI_IMR
Offset: 0x1C
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
       TOUT  
Access R 
Reset 0 
Bit 15141312111098 
 CSRACSFAQITRQITFLWRAINSTRE CSR 
Access RRRRRRR 
Reset 0000000 
Bit 76543210 
 TXBUFERXBUFFENDTXENDRXOVRESTXEMPTYTDRERDRF 
Access RRRRRRRR 
Reset 00000000 

Bit 17 – TOUT QSPI Time-out Interrupt Mask

Bit 15 – CSRA Chip Select Rise Autoclear Interrupt Mask

Bit 14 – CSFA Chip Select Fall Autoclear Interrupt Mask

Bit 13 – QITR QSPI Interrupt Rise Interrupt Mask

Bit 12 – QITF QSPI Interrupt Fall Interrupt Mask

Bit 11 – LWRA Last Write Access Interrupt Mask

Bit 10 – INSTRE Instruction End Interrupt Mask

Bit 8 – CSR Chip Select Rise Interrupt Mask

Bit 7 – TXBUFE Transmit Buffer Empty Interrupt Mask

Bit 6 – RXBUFF Receive Buffer Full Interrupt Mask

Bit 5 – ENDTX End of Transmit Buffer Interrupt Mask

Bit 4 – ENDRX End of Receive Buffer Interrupt Mask

Bit 3 – OVRES Overrun Error Interrupt Mask

Bit 2 – TXEMPTY Transmission Registers Empty Mask

Bit 1 – TDRE Transmit Data Register Empty Interrupt Mask

Bit 0 – RDRF Receive Data Register Full Interrupt Mask