35.7.6 QSPI Interrupt Enable Register

This register can only be written if the WPITEN bit is cleared in the QSPI Write Protection Mode Register.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Enables the corresponding interrupt.

Name: QSPI_IER
Offset: 0x14
Reset: –
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
       TOUT  
Access W 
Reset – 
Bit 15141312111098 
 CSRACSFAQITRQITFLWRAINSTRE CSR 
Access WWWWWWW 
Reset ––––––– 
Bit 76543210 
 TXBUFERXBUFFENDTXENDRXOVRESTXEMPTYTDRERDRF 
Access WWWWWWWW 
Reset –––––––– 

Bit 17 – TOUT QSPI Time-out Interrupt Enable

Bit 15 – CSRA Chip Select Rise Autoclear Interrupt Enable

Bit 14 – CSFA Chip Select Fall Autoclear Interrupt Enable

Bit 13 – QITR QSPI Interrupt Rise Interrupt Enable

Bit 12 – QITF QSPI Interrupt Fall Interrupt Enable

Bit 11 – LWRA Last Write Access Interrupt Enable

Bit 10 – INSTRE Instruction End Interrupt Enable

Bit 8 – CSR Chip Select Rise Interrupt Enable

Bit 7 – TXBUFE Transmit Buffer Empty Interrupt Enable

Bit 6 – RXBUFF Receive Buffer Full Interrupt Enable

Bit 5 – ENDTX End of Transmit Buffer Interrupt Enable

Bit 4 – ENDRX End of Receive Buffer Interrupt Enable

Bit 3 – OVRES Overrun Error Interrupt Enable

Bit 2 – TXEMPTY Transmission Registers Empty Enable

Bit 1 – TDRE Transmit Data Register Empty Interrupt Enable

Bit 0 – RDRF Receive Data Register Full Interrupt Enable