35.7.7 QSPI Interrupt Disable Register

This register can only be written if the WPITEN bit is cleared in the QSPI Write Protection Mode Register.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Disables the corresponding interrupt.

Name: QSPI_IDR
Offset: 0x18
Reset: –
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
       TOUT  
Access W 
Reset – 
Bit 15141312111098 
 CSRACSFAQITRQITFLWRAINSTRE CSR 
Access WWWWWWW 
Reset ––––––– 
Bit 76543210 
 TXBUFERXBUFFENDTXENDRXOVRESTXEMPTYTDRERDRF 
Access WWWWWWWW 
Reset –––––––– 

Bit 17 – TOUT QSPI Time-out Interrupt Disable

Bit 15 – CSRA Chip Select Rise Autoclear Interrupt Disable

Bit 14 – CSFA Chip Select Fall Autoclear Interrupt Disable

Bit 13 – QITR QSPI Interrupt Rise Interrupt Disable

Bit 12 – QITF QSPI Interrupt Fall Interrupt Disable

Bit 11 – LWRA Last Write Access Interrupt Disable

Bit 10 – INSTRE Instruction End Interrupt Disable

Bit 8 – CSR Chip Select Rise Interrupt Disable

Bit 7 – TXBUFE Transmit Buffer Empty Interrupt Disable

Bit 6 – RXBUFF Receive Buffer Full Interrupt Disable

Bit 5 – ENDTX End of Transmit Buffer Interrupt Disable

Bit 4 – ENDRX End of Receive Buffer Interrupt Disable

Bit 3 – OVRES Overrun Error Interrupt Disable

Bit 2 – TXEMPTY Transmission Registers Empty Disable

Bit 1 – TDRE Transmit Data Register Empty Interrupt Disable

Bit 0 – RDRF Receive Data Register Full Interrupt Disable