35.7.10 QSPI Status Register
| Name: | QSPI_SR |
| Offset: | 0x24 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HIDLE | RBUSY | CSS | QSPIENS | SYNCBSY | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 4 – HIDLE QSPI Idle
| Value | Description |
|---|---|
| 0 | The QSPI is not in Idle state (either transmitting or Chip Select is active). |
| 1 | The QSPI is in Idle state (not transmitting and Chip Select is inactive). |
Bit 3 – RBUSY Read Busy
| Value | Description |
|---|---|
| 0 | The system bus interface has no activity. |
| 1 | The system bus interface is currently processing accesses. |
Bit 2 – CSS Chip Select Status
| Value | Description |
|---|---|
| 0 | The chip select is asserted. |
| 1 | The chip select is not asserted. |
Bit 1 – QSPIENS QSPI Enable Status
| Value | Description |
|---|---|
| 0 | The QSPI is disabled. |
| 1 | The QSPI is enabled. |
Bit 0 – SYNCBSY Synchronization Busy
| Value | Description |
|---|---|
| 0 | No event synchronization between the QSPI Controller interface and QSPI Controller core is ongoing. Register accesses requiring synchronization are allowed, see Register Synchronization. |
| 1 | Event synchronization between the QSPI Controller interface and QSPI Controller core is ongoing. Register accesses requiring synchronization are not allowed, see Register Synchronization. |