1.1.8.4.19 DRV_SPI_CLOCK_PHASE Enum

typedef enum
{
    /* Input data is valid on clock trailing edge and
    output data is ready on leading edge */
    DRV_SPI_CLOCK_PHASE_VALID_TRAILING_EDGE,

    /* Input data is valid on clock leading edge and
    output data is ready on trailing edge */
    DRV_SPI_CLOCK_PHASE_VALID_LEADING_EDGE

}DRV_SPI_CLOCK_PHASE;

Identifies SPI Clock Phase Options

This enumeration identifies possible SPI Clock Phase Options.

None.