1.3.1 Memory and Peripheral Address Map
(Ask a Question)This section lists the memory and peripheral address map of the Root Port demo design.
The address maps of the Mi-V peripherals and main memory are:
- APB interface: 0x60000000 to 0x6FFFFFFF
- AXI interface: 0x70000000 to 7FFFFFFF
- TCM memory interface : 0x80000000 to 0x8FFFFFFF.
The following table lists the address map of the Bus interfaces connecting Mi-V to PF_PCIE.
| Bus Interface/Component | Description | Memory Map |
|---|---|---|
| PCIe_APB | This bus interface is used to access the PCIe register | 0x63000000 to 0x63FFFFFF |
| MIV_ESS_C0 UART | This block establishes a UART interface to connect the Mi-V processor to the external world | 0x61000000 to 0x61FFFFFF |
| PCIE_1_PERST_OUT_N | This is used to generate the PERSTn signal for the link partner that is connected to the Root port | 0x6300A150 |
| PCIe_AXI | This Bus interface is the PCIe AXI slave for EP configuration or BAR space access | 0x70000000 to 0x7000FFFF—Configuration space (Mi-V configures through PCIe APB) 0x71000000 to 0x7100FFFF—EP BAR0 space 0x72000000 to 0x7200FFFF—EP BAR2 space 0x73000000 to 0x73FFFFFF—RP AXI Master—LSRAM/DDR4 (Mi-V configures through PCIe APB) |
| TCM | This block is the main memory of the Mi-V processor | 0x80000000 to 0x8FFFFFFF |
The PF_PCIE block connects to the DDR4 and LSRAM blocks through the AXI_1_master Bus interface. The address maps of DDR4 and LSRAM are 0x10000000 to 0x1FFFFFFF and 0x00000000 to 0x00000FFF, respectively.