1.3.2 Design Implementation

The following figure shows the Libero SoC software design implementation of the PCIe Root Port demo design.

Figure 1-2. PCIe Root Port Demo Design

The top-level design includes the following SmartDesign components and memory controller subsystems:

  • MIV_SS_0
  • PCIe_RP_0
  • DDR4
    Important: PERSTn is a fundamental reset signal defined in both PCI Express Base Specification and PCI Express Card Electromechanical Specification. It is a reset signal issued by the Root port through PCIe slots to reset the entire PCIe fabric hierarchy. The Root port firmware running on the MI-V processor can assert the PERSTn signal through PCIE_APB_SLAVE interface. When the host is power cycled, the PERSTn signal is asserted by the PCIe_INIT_MONITOR_0 until the PCIe controller in the Root port is initialized.