7.1 1G Ethernet BASE-T and BASE-X

The following figure shows the typical FPGA design for 1G Ethernet BASE-T.
Figure 7-1. 1G BASE-T Design
The following figure shows the typical FPGA design for 1G Ethernet BASE-X.
Figure 7-2. 1G BASE-X Design

The following points summarize the 1G Ethernet BASE-T and BASE-X designs:

  • The Mi-V soft processor is used to configure the PHY registers (using MDIO interface), the MAC Configuration, and the Management registers. Users can also implement a fabric logic or any other soft processor to implement these functions.
  • The MAC IP is configured in the TBI mode.
  • In BASE-T, the management block of the MAC IP auto-negotiates with the onboard PHY as per Clause 28 of the IEEE802.3z standard. The PHY auto-negotiates with the link partner.
  • In BASE-X, the management block of the MAC IP auto-negotiates with the link partner as per Clause 37 of the IEEE802.3z standard.
  • The Auto-Negotiation (AN) functions are defined in the MAC Management registers 04h to 08h. The bit field formats of these registers are different for BASE-T and BASE-X. For more information about the bit field formats of the AN registers, see HB0549: CoreTSE v3.1 Handbook or HB0627: CoreSGMII v3.2 Handbook from the Libero SoC Catalog. The following table lists the AN registers.
    Table 7-1. AN Registers
    RegisterDescription
    04hAN Advertisement
    05hAN Link Partner Base Page Ability
    06hAN Expansion
    07hAN Next Page Transmit
    08hAN Link Partner Ability Next Page

    The following registers are common in BASE-T and BASE-X modes:

    • Control register at address 0x00
    • Status register at address 0x01

Registers 0x04, 0x05, 0x06, 0x07, and 0x08 are based on the configuration.

  • XCVR is configured to operate at 1250 Mbps. For more information about XCVR configuration, see Transceiver Configuration
  • The user data from MAC (CoreTSE non-AHB) is provided on a 32-bit parallel bus