7.2 Transceiver Configuration

For 1G Ethernet BASE-T and BASE-X, the transceiver block is configured for 1.25 Gbps data rate. Figure 7-3 shows the configuration of the transceiver block in the Libero SoC design suite. The following table lists the transceiver configuration.

Table 7-2. XCVR Configuration
ParametersSettings
Number of lanes1
Data Rate1250 Mbps
PMA
TX clock division factor4
TX PLL base data rate5000 Mbps
TX PLL bit clock frequency2500 Mbps
CDR lock modelock to data
CDR reference clock sourceDedicated
CDR reference clock frequency125 MHz
PCS
PCS-fabric interface width10 bits
FPGA interface frequency125 MHz
PMA ModeEnabled
Clocks and Resets
TX clockRegional
RX clockRegional
PCS ResetRX Only
Figure 7-3. Transceiver Configuration