25.8.1 Control A
| Name: | CTRLA |
| Offset: | 0x0 |
| Reset: | 0x0004 |
| Property: | PAC Write-Protection |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CACHEDIS1 | CACHEDIS0 | AHBNS1 | AHBNS0 | RWS[3:0] | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PRM[1:0] | WMODE[1:0] | SUSPEN | AUTOWS | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 1 | |||
Bit 15 – CACHEDIS1 AHB1 Cache Disable
AHB1 interface cache disable.
0: cache line is enabled
1: cache line is disabled
Cache lines are automatically invalidated when a write or erase operation is started in the NVM.
Bit 14 – CACHEDIS0 AHB0 Cache Disable
AHB0 interface cache disable.
0: cache line is enabled
1: cache line is disabled
Cache lines are automatically invalidated when a write or erase operation is started in the NVM.
Bit 13 – AHBNS1 Force AHB1 access to Non-Sequential
| Value | Description |
|---|---|
| 0 | AHB sequential accesses remain sequential. |
| 1 | AHB sequential accesses are forced to non-sequential, therefore forcing rearbitration for each access. |
Bit 12 – AHBNS0 Force AHB0 access to Non-Sequential
| Value | Description |
|---|---|
| 0 | AHB sequential accesses remain sequential. |
| 1 | AHB sequential accesses are forced to non-sequential, therefore forcing rearbitration for each access. |
Bits 11:8 – RWS[3:0] NVM Read Wait States
These bits give the number of wait states for a read operation when AUTOWS=0. Zero indicates zero wait states, one indicates one wait state, etc., up to 15 wait states.
This register is initialized to 0 wait states. Software can change this value based on the NVM access time and system frequency.
Bits 7:6 – PRM[1:0] Power Reduction Mode during Sleep
| Value | Name | Description |
|---|---|---|
| 0x0 | SEMIAUTO | NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. |
| 0x1 | FULLAUTO | NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode. |
| 0x2 | Reserved | |
| 0x3 | MANUAL | NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. |
Bits 5:4 – WMODE[1:0] Write Mode
| Value | Name | Description |
|---|---|---|
| 0x0 | MAN | Manual Write |
| 0x1 | ADW | Automatic Double Word Write |
| 0x2 | AQW | Automatic Quad Word |
| 0x3 | AP | Automatic Page Write |
Bit 3 – SUSPEN Suspend Enable
0: The write and erase suspend resume feature is disabled.
1: A write or erase operation can be suspended in case of a read in the same bank.
Bit 2 – AUTOWS Auto Wait State Enable
0: Automatic wait state generation is disabled. The number of wait states used is given by CTRLA.RWS bits.
1: Automatic wait state generation is enabled. The number of wait states used is automatically detected therefore the module can operate at any frequency up to the device maximum frequency. A minimum of one cycle latency is induced.