25.8.2 Control B
| Name: | CTRLB |
| Offset: | 0x04 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CMDEX[7:0] | |||||||||
| Access | PAC Write-Protection | PAC Write-Protection | PAC Write-Protection | PAC Write-Protection | PAC Write-Protection | PAC Write-Protection | PAC Write-Protection | PAC Write-Protection | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CMD[6:0] | |||||||||
| Access | W | W | W | W | W | W | W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 15:8 – CMDEX[7:0] Command Execution
This bit group should be written with the key value 0xA5 to enable the command written to CMD to be executed. If the bit group is written with a different key value, the write is not performed and INTFLAG.PROGE is set. PROGE is also set if the a previously written command is not complete.
The key value must be written at the same time as CMD. If a command is issued through the APB bus on the same cycle as an AHB bus access, the AHB bus access will be given priority. The command will then be executed when the NVM block and the AHB bus are idle.
STATUS.READY must be one when the command is issued.
INTFLAG.DONE is set when the command completes.
| Value | Name | Description |
|---|---|---|
| 0xA5 | KEY | Execution Key |
| Other | - | Reserved |
Bits 6:0 – CMD[6:0] Command
| Value | Name | Description |
|---|---|---|
| 0x0 | EP | Erase Page - Only supported in the User page in the auxiliary space. |
| 0x1 | EB | Erase Block - Erases the block addressed by the ADDR register, not supported in the user page |
| 0x2 | Reserved | |
| 0x3 | WP | Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page |
| 0x4 | WQW | Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register. |
| 0x5-0xF | Reserved | |
| 0x10 | SWRST | Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers |
| 0x11 | LR | Lock Region - Locks the region containing the address location in the ADDR register until next reset. |
| 0x12 | UR | Unlock Region - Unlocks the region containing the address location in the ADDR register until next reset. |
| 0x13 | SPRM | Sets the power reduction mode. |
| 0x14 | CPRM | Clears the power reduction mode. |
| 0x15 | PBC | Page Buffer Clear - Clears the page buffer. |
| 0x16 | SSB | Set Security Bit |
| 0x17 | BKSWRST | Bank swap and system reset, if SmartEEPROM is used also reallocate its data into the opposite BANK |
| 0x18 | CELCK | Chip Erase Lock - DSU CTRL.CE command is not available. As soon as the CELCK command is successfully executed, the chip erase capability is disabled and Microchip’s failure analysis capabilities are limited. Therefore, the software has to ensure there is a way to unlock the chip erase by executing the CEULCK command. |
| 0x19 | CEULCK | Chip Erase Unlock - The DSU CTRL.CE command is available. |
| 0x1A | SBPDIS | Sets STATUS.BPDIS, bootloader protection is discarded until CBPDIS is issued or next start-up sequence. |
| 0x1B | CBPDIS | Clears STATUS.BPDIS, bootloader protection is not discarded. |
| 0x1C-0x2F | Reserved | |
| 0x30 | ASEES0 | Configure SmartEEPROM to use Sector 0 |
| 0x31 | ASEES1 | Configure SmartEEPROM to use Sector 1 |
| 0x32 | SEERALOC | Starts SmartEEPROM sector reallocation algorithm |
| 0x33 | SEEFLUSH | Flush SmartEEPROM data when in buffered mode |
| 0x34 | LSEE | Lock access to SmartEEPROM data from any means |
| 0x35 | USEE | Unlock access to SmartEEPROM data |
| 0x36 | LSEER | Lock access to the SmartEEPROM Register Address Space (above 64KB) |
| 0x37 | USEER | Unock access to the SmartEEPROM Register Address Space (above 64KB) |
| 0x38-0x7F | Reserved |