25.8.6 Interrupt Flag Status and Clear
| Name: | INTFLAG |
| Offset: | 0x10 |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SEEWRC | SEESOVF | SEESFULL | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SUSP | NVME | ECCDE | ECCSE | LOCKE | PROGE | ADDRE | DONE | ||
| Access | R/W | R/W | R | R | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 10 – SEEWRC SEE Write Completed
- Unbuffered mode:
0: AHB write is pending.
1: AHB write has completed, and NVM is programmed with correct values.
- Buffered mode:
0: AHB write is pending.
1: AHB write has completed.
If SEESTAT.LOAD=0, then the NVM is programmed with correct values.
If SEESTAT.LOAD=1, then data is still pending in the Page Buffer.
Bit 9 – SEESOVF Active SEES Overflow
0: No SEES overflow have been detected since the last clear.
1: At least SEES overflow has been detected since the last clear.
This bit can be cleared by writing a one to its bit location.
Bit 8 – SEESFULL Active SEES Full
0: The active SEES is not full
1: The active SEES is Full, meaning that the next write will fail if the active sector is not reallocated.
This bit can be cleared by writing a one to its bit location.
Bit 7 – SUSP Suspended Write Or Erase Operation
0: No write/suspend has occurred since the last clear.
1: A write or erase operation has been suspended since the last clear.
This bit can be cleared by writing a one to its bit location.
Bit 6 – NVME NVM Error
0: No NVM errors have been received since the last clear.
1: At least one NVM error has occurred since the last clear.
This bit can be cleared by writing a one to its bit location.
Bit 5 – ECCDE ECC Dual Error
0: No ECC dual errors have been received since the last ECCERR register read.
1: At least one ECC error has occurred since the last ECCERR register read.
This bit is cleared when the ECCERR register is read.
Bit 4 – ECCSE ECC Single Error
0: No ECC single errors have been received since the last ECCERR register read.
1: At least one ECC error has occurred since the last ECCERR register read.
This bit is cleared when the ECCERR register is read.
Bit 3 – LOCKE Lock Error
0: No LOCK errors have been received since the last clear.
1: At least one LOCK error has occurred since the last clear.
This bit can be cleared by writing a one to its bit location.
Bit 2 – PROGE Programming Error
0: No PROG errors have been received since the last clear.
1: At least one PROG error has occurred since the last clear.
This bit can be cleared by writing a one to its bit location.
Bit 1 – ADDRE Address Error
0: No ADDRE error has been detected since the last clear.
1: At least one ADDRE error has been detected since the last clear.
This bit can be cleared by writing a one to its bit location.
Bit 0 – DONE Command Done
0: The NVM controller has not completed any command since the last clear.
1: At least one command has completed since the last clear.
This bit can be cleared by writing a one to its bit location.