56.7.5 Fractional Digital Phase Lock Loop (FDPLL) Characteristics (125°C)

Table 56-28. Fractional Digital Phase Lock Loop Characteristics (1)
SymbolParameterConditionsMin.Typ.Max.Units
Jp Period jitter (Peak-Peak value)fIN = 32 kHz, fOUT = 96 MHz -1.9 3.0%
fIN = 32 kHz, fOUT = 200 MHz -3.4 6.0
fIN = 3.2 MHz, fOUT = 96 MHz -2.0 3.1
fIN = 3.2 MHz, fOUT = 200 MHz -4.3 7.2
Note:
  1. These FDPLL200Mn characteristics are applicable with LDO regulator and a direct reference (i.e., REFCLK is XOSC or XOSC32K, not GCLK).
Table 56-29. Fractional Digital Phase Lock Loop Power Consumption
SymbolParameterConditionsTATyp.Max.Units
IDDCurrent Consumption Ck = 96 MHz, VDD = 3.3VMax. 125°C

Typ. 25°C

0.92.5mA
Ck = 200 MHz, VDD = 3.3V2.03.4