54.13.4 Digital Frequency Locked Loop (DFLL48M) Characteristics

Table 54-50. DFLL48M Characteristics - Open Loop Mode ⁽¹⁾
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
F_OpenOUT	Output frequency	DFLLVAL after Reset LDO Regulator mode, [-40, 85]°C	45.8	48	49.3	MHz
F_OpenOUT	Output frequency	DFLLVAL after Reset LDO Regulator mode, [0, 60]°C	47.2	48	48.81	MHz
T_OpenSTARTUP	Startup time	DFLLVAL after Reset F_OUT within 90% of final value	-	4.3	7	µs

Note:

DFLL48 in open loop can be used only with LDO regulator.

Table 54-51. DFLL48M Characteristics - Closed Loop Mode
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
F_CloseOUT	Average Output frequency	f_REF = XTAL, 32.768 kHz, 100 ppm DFLLMUL = 1464	-	47.972	-	MHz
F_REF^(1,2)	Input reference frequency	-	732	32768	33000	Hz
F_CloseJitter	Period Jitter	f_REF = XTAL, 32.768 kHz, 100 ppm DFLLMUL = 1464	-	-	0.42	ns
T_Lock	Lock time	F_REF = XTAL, 32.768 kHz, 100 ppm DFLLMUL = 1464 DFLLVAL after Reset DFLLCTRL.BPLCKC = 1 DFLLCTRL.QLDIS = 0 DFLLCTRL.CCDIS = 1 DFLLMUL.FSTEP = 10	-	429	1145	µs

Note:

These values are based on simulation. They are not covered by production test limits or characterization.
To ensure that the device stays within the maximum allowed clock frequency, any reference clock for the DFLL in close loop must be within 2% error accuracy.

Table 54-52. DFLL48M Power Consumption
Symbol	Parameter	Conditions	Ta	Min.	Typ.	Max.	Units
I_DD	Current Consumption	Open Loop mode - DFLLVAL after reset VDD = 3.3V	Max. 85°C Typ. 25°C	-	404	854	µA
I_DD	Current Consumption	Closed Loop mode - f_REF = 32 .768 kHz VDD = 3.3V	Max. 85°C Typ. 25°C	-	404	854	µA

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