2.10 UART
A UART Transmit Interrupt (UTXISEL[1:0] bits = ‘0b01) is generated but
does not remain asserted even after all of the characters were transmitted. When the
IFSx bit is cleared by the user, it does not remain asserted even after all characters
were transmitted. This behavior, compounded with finite interrupt latency, can create a
race condition amongst subsequent TX interrupts.
Work Around
To avoid the race condition, clear the UARTx IFSx flag before writing a new value to the TX Buffer, UxTXREG, in the ISR.
Affected Silicon Revisions
| A0 | A1 | B0 | C0 |
|---|---|---|---|
| X | X | X | X |