6.1 DDR3

The following are the guidelines for connecting the device to the DDR3 memory:

  • DDR3 data nets have dynamic ODT built into the controller and SDRAM. The configurations are 60Ω, and 120Ω. DQ lines do not need VTT termination. However, VTT termination resistors need to be placed at the end of address and control lines on the PCB.
  • Characteristic impedance: ZO is typically 50Ω, and Zdiff (differential) is 100Ω.

The following table lists the DDR3 memory interface features supported in PolarFire devices.

Table 6-2. Interfaces Supported in DDR3 Memory Devices
InterfaceDDR3
Voltage1.5V
I/O standardSSTL_15
Data rate1333 MT/S-HSIO and 1066 MT/S-GPIO
TerminationODT for data group; VTT termination for address, command, and control
Routing topology (CK, ADDR/CMD, and CONTROL)Fly-by
Data transmissionPoint-to-point

The following figure shows the connectivity between DDR3 devices and PolarFire FPGAs.

Figure 6-1. DDR3 Interface Example