6.1.1 DDR3 Layout Guidelines
(Ask a Question)This section describes the routing guidelines for DDR3 interface for PolarFire Family. The guidelines are with reference to maximum x72 data width from signal integrity perspective. All the guidelines are provided considering maximum data rate supported. It is recommended to evaluate the interface by performing system level signal integrity simulations. The user is assumed to have the knowledge of the memory interface guidelines.
| Clock Signal | Description |
|---|---|
| CK0:1 P/N | Differential clock signals |
| Control signals | |
| CS | Chip Select |
| CKE | Clock Enable |
| ODT | On Die termination enable |
| Reset_n | Reset signal |
| Address Signal | |
| A[15:0] | Address Signals |
| BA[2:0] | Bank address |
| Command Signal | |
| RAS_n | Row address select |
| CAS_n | Column address select |
| WE_n | Write enable |
| Data signals | |
| DQ[71:0] | Data bit |
| DQM[8:0] | Data mask |
| DQS_P/N[8:0] | Data strobe |
Due to high speed signaling, DDR3 uses fly-by routing topology for Address, Command, Control signals to achieve best performance. As shown in the following figure, the ADDR/CMD are routed as single-ended in fly-by topology. It is recommended to have all the signals being routed in one signal layer to control the skew within the signal groups. The DQ/DQS signals being point to point signals, uses on die termination on memory and FPGA side.
DQ bit swapping within a byte lane is supported on the PCB between the DDR controller and the DDR3 memory for routing flexibility.