6.3 DDR4

The following are the guidelines for connecting the device to the DDR4 memory:

  • DDR4 data nets have dynamic ODT built into the controller and SDRAM. The configurations are 80Ω, 120Ω, and 240Ω. DQ lines do not need VTT termination. However, VTT termination resistors need to be placed at the end of address and control lines on the PCB.
  • Characteristic impedance: Z0 is typically 50Ω and Zdiff (differential) is 100Ω.

The following figure shows the features supported by PolarFire FPGA in the DDR4 memory interface.

Figure 6-8. DDR4 Interface Example
Note: Each address and command line should use fly-by routing to VTT at the end of the net. Termination resistor (RT) value, between 30–50Ω, is typically used for this. The user must simulate to optimize and ensure that optimal termination resistor (RT) value is used.