52.6.11 TZAESB Write Protection Status Register
| Name: | TZAESB_WPSR |
| Offset: | 0xE8 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ECLASS | SWETYP[3:0] | ||||||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WPVSRC[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PKRPVS | SWE | SEQE | CGD | WPVS | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 31 – ECLASS Software Error Class (cleared on read)
| Value | Name | Description |
|---|---|---|
| 0 | WARNING | An abnormal access that does not affect system functionality |
| 1 | ERROR | An access is performed into key, input data, control registers while the TZAESB is performing an encryption/decryption or a start is request by software or DMA while the key is not fully configured. |
Bits 27:24 – SWETYP[3:0] Software Error Type (cleared on read)
| Value | Name | Description |
|---|---|---|
| 0 | READ_WO | A write-only register has been read (Warning). |
| 1 | WRITE_RO | TZAESB is enabled and a write access has been performed on a read-only register (Warning). |
| 2 | UNDEF_RW | Access to an undefined address (Warning). |
| 3 | CTRL_START | Abnormal use of TZAESB_CR.START command when DMA access is configured. |
| 4 | WEIRD_ACTION | A Private Key bus access, key write, init value write, output data read or TZAESB_MR and TZAESB_EMR write has been performed while a process is in progress (abnormal). |
| 5 | INCOMPLETE_KEY | A tentative of start is required while the key is not fully loaded into the TZAESB_KEYWRx registers. |
Bits 15:8 – WPVSRC[7:0] Write Protection Violation Source
When WPVS=1, WPVSRC indicates the register address offset at which a write access has been attempted.
When WPVS=0 and SWE=1, WPVSRC reports the address of the incorrect software access. As soon as WPVS=1, WPVSRC returns the address of the write-protected violation.
Bit 4 – PKRPVS Private Key Internal Register Protection Violation Status (cleared on read)
| Value | Description |
|---|---|
| 0 | No Private Key internal register access violation has occurred since the last read of TZAESB_WPSR. |
| 1 | A Private Key internal register access violation has occurred since the last read of TZAESB_WPSR. |
Bit 3 – SWE Software Control Error (cleared on read)
| Value | Description |
|---|---|
| 0 | No software error has occurred since the last read of TZAESB_WPSR. |
| 1 | A software error has occurred since the last read of TZAESB_WPSR. The field SWETYP details the type of software error; the associated incorrect software access is reported in the field WPVSRC (if WPVS=0). |
Bit 2 – SEQE Internal Sequencer Error (cleared on read)
| Value | Description |
|---|---|
| 0 | No peripheral internal sequencer error has occurred since the last read of TZAESB_WPSR. |
| 1 | A peripheral internal sequencer error has occurred since the last read of TZAESB_WPSR. This flag can only be set under abnormal operating conditions. |
Bit 1 – CGD Clock Glitch Detected (cleared on read)
| Value | Description |
|---|---|
| 0 | No clock glitch has occurred since the last read of TZAESB_WPSR. Under normal operating conditions, this bit is always cleared. |
| 1 | A clock glitch has occurred since the last read of TZAESB_WPSR. This flag can only be set in case of an abnormal clock signal waveform (glitch). |
Bit 0 – WPVS Write Protection Violation Status (cleared on read)
| Value | Description |
|---|---|
| 0 | No write protect violation has occurred since the last read of TZAESB_WPSR. |
| 1 | A write protect violation has occurred since the last read of TZAESB_WPSR. The address offset of the violated register is reported into field WPVSRC. |