52.6.6 TZAESB Interrupt Status Register
| Name: | TZAESB_ISR |
| Offset: | 0x1C |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SECE | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| URAT[3:0] | URAD | ||||||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bit 19 – SECE Security and/or Safety Event
| Value | Description |
|---|---|
| 0 | There is no security report in TZAESB_WPSR. |
| 1 | One security flag is set in TZAESB_WPSR. |
Bits 15:12 – URAT[3:0] Unspecified Register Access
Only the last Unspecified Register Access Type is available through URAT.
URAT is reset only by TZAESB_CR.SWRST.
| Value | Name | Description |
|---|---|---|
| 0 | IDR_WR_PROCESSING | Input Data register written during the data processing |
| 1 | ODR_RD_PROCESSING | Output Data register read during the data processing |
| 2 | MR_WR_PROCESSING | Mode register written during the data processing |
| 3 | ODR_RD_SUBKGEN | Output Data register read during the sub-keys generation |
| 4 | MR_WR_SUBKGEN | Mode register written during the sub-keys generation |
| 5 | WOR_RD_ACCESS | Write-only register read access |
Bit 8 – URAD Unspecified Register Access Detection Status
URAD is reset only by TZAESB_CR.SWRST.
| Value | Description |
|---|---|
| 0 | No unspecified register access has been detected since the last SWRST. |
| 1 | At least one unspecified register access has been detected since the last SWRST. |