52.6.10 TZAESB Write Protection Mode Register

Name: TZAESB_WPMR
Offset: 0xE4
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
 WPKEY[23:16] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 WPKEY[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 WPKEY[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 ACTION[2:0]FIRSTE WPCRENWPITENWPEN 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bits 31:8 – WPKEY[23:0] Write Protection Key

ValueNameDescription
0x414553 PASSWD

Writing any other value in this field aborts the write operation of the WPEN,WPITEN,WPCREN bits.

Always reads as 0.

Bits 7:5 – ACTION[2:0] Action on Abnormal Event Detection

ValueNameDescription
0 REPORT_ONLY

No action (stop or clear key) is performed when one of PKRPVS, WPVS, CGD, SEQE, or SWE flags is set.

1 LOCK_PKRPVS_WPVS_SWE

If a processing is in progress when the TZAESB_WPSR.PKRPVS/WPVS/SWE event detection occurs, the current processing is ended normally but no other processing is started while a TZAESB_CR.UNLOCK command is issued.

2 LOCK_CGD_SEQE

If a processing is in progress when the TZAESB_WPSR.CGD/SEQE event detection occurs, the current processing is ended normally but no other processing is started while a TZAESB_CR.UNLOCK command is issued.

3 LOCK_ANY_EV

If a processing is in progress when the TZAESB_WPSR.PKRPVS/WPVS/CGD/SEQE/SWE events detection occurs, the current processing is ended normally but no other processing is started while a TZAESB_CR.UNLOCK command is issued.

4 CLEAR_PKRPVS_WPVS_SWE

If a processing is in progress when the TZAESB_WPSR.PKRPVS/WPVS/SWE events detection occurs, the current processing is ended normally but no other processing is started while a TZAESB_CR.UNLOCK command is issued.

Moreover, the TZAESB_KEYWRx key is immediately cleared.

5 CLEAR_CGD_SEQE

If a processing is in progress when the TZAESB_WPSR.CGD/SEQE events detection occurs, the current processing is ended normally but no other processing is started while a TZAESB_CR.UNLOCK command is issued.

Moreover, the TZAESB_KEYWRx key is immediately cleared.

6 CLEAR_ANY_EV

If a processing is in progress when the TZAESB_WPSR.PKRPVS/WPVS/CGD/SEQE/SWE events detection occurs, the current processing is ended normally but no other processing is started while a TZAESB_CR.UNLOCK command is issued.

Moreover, the TZAESB_KEYWRx key is immediately cleared.

Bit 4 – FIRSTE First Error Report Enable

ValueDescription
0

The last write protection violation source is reported in TZAESB_WPSR.WPVSRC and the last software control error type is reported in TZAESB_WPSR.SWETYP. The TZAESB_ISR.SECE flag is set at the first error occurrence within a series.

1

Only the first write protection violation source is reported in TZAESB_WPSR.WPVSRC and only the first software control error type is reported in TZAESB_WPSR.SWETYP. The TZAESB_ISR.SECE flag is set at the first error occurrence within a series.

Bit 2 – WPCREN Write Protection Control Enable

ValueDescription
0

Disables the write protection on control register if WPKEY corresponds to 0x414553 (“AES” in ASCII).

1

Enables the write protection on control register if WPKEY corresponds to 0x414553 (“AES” in ASCII).

Bit 1 – WPITEN Write Protection Interruption Enable

ValueDescription
0

Disables the write protection on interrupt registers if WPKEY corresponds to 0x414553 (“AES” in ASCII).

1

Enables the write protection on interrupt registers if WPKEY corresponds to 0x414553 (“AES” in ASCII).

Bit 0 – WPEN Write Protection Configuration Enable

See Register Write Protection for the list of registers that can be write-protected.

ValueDescription
0

Disables the write protection on configuration registers if WPKEY corresponds to 0x414553 (“AES” in ASCII).

1

Enables the write protection on configuration registers if WPKEY corresponds to 0x414553 (“AES” in ASCII).