52.6.3 TZAESB Interrupt Enable Register
This register can only be written if WPITEN is cleared in the TZAESB Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
| Name: | TZAESB_IER |
| Offset: | 0x10 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SECE | |||||||||
| Access | W | ||||||||
| Reset | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| URAD | |||||||||
| Access | W | ||||||||
| Reset | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |