52.6.2 TZAESB Mode Register
This register can only be written if WPEN is cleared in the TZAESB Write Protection Mode Register.
| Name: | TZAESB_MR |
| Offset: | 0x04 |
| Reset: | 0x00000004 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TAMPCLR | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CKEY[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| OPMOD[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PROCDLY[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bit 31 – TAMPCLR Tamper Clear Enable
| Value | Description |
|---|---|
| 0 | A tamper detection event has no effect on the TZAESB_KEYWRx key. |
| 1 | A tamper detection event immediately clears the TZAESB_KEYWRx key. |
Bits 23:20 – CKEY[3:0] Key
| Value | Name | Description |
|---|---|---|
| 0xE | PASSWD | Must be written with 0xE the first time that TZAESB_MR is programmed. For subsequent programming of TZAESB_MR, any value can be written, including that of 0xE. Always reads as 0. |
Bits 14:12 – OPMOD[2:0] Operating Mode
Values which are not listed in the table must be considered as “reserved”.
| Value | Name | Description |
|---|---|---|
| 0 | – | Reserved |
| 1 | – | Reserved |
| 2 | – | Reserved |
| 3 | – | Reserved |
| 4 | CTR | Counter mode (16-bit internal counter) |
Bits 7:4 – PROCDLY[3:0] Processing Delay
Processing Time = 12 × (PROCDLY + 1)
The Processing Time represents the number of clock cycles that the TZAESB needs in order to perform one encryption/decryption .