17.5.13 2T Memory Command Timing

Memory command duration is one memory clock cycle, which is referred to as 1T command timing.

Optionally, to provide sufficient address setup time in heavily loaded memory bus configurations, memory address and memory command are asserted for two memory clock cycles which is referred to as 2T command timing.

Figure 17-5. 1T Memory Command Timing

Figure 17-6. 2T Memory Command Timing

Note:

2T mode is not supported when BL2 is selected.
2T mode is not supported in LPDDR2/LPDDR3 modes.

Enabling 2T Memory Command Timing:

This feature is enabled using the register MSTR.en_2t_timing_mode.

For more information about these registers, see Register Descriptions.

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