17.5.12 Mode Register Reads and Writes

This section explains how to perform mode register reads and writes through software. Mode Register Reads (MRR) are applicable only to LPDDR2/LPDDR3, and are used to read configuration and status data from mode registers in the SDRAM. Mode Register Writes (MRW or MRS) are applicable to all supported DDR protocols, and are used to write configuration data to mode registers in the SDRAM. Access to the mode register is initiated by programming the MRCTRL0 and MRCTRL1 registers (see Register Descriptions). This must be done in three steps:

1. Poll MRSTAT.mr_wr_busy until it is ‘0’. This checks that there is no outstanding MR transaction. No writes should be performed to MRCTRL0 and MRCTRL1 if MRSTAT.mr_wr_busy = 1.
2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and (for MRWs) MRCTRL1.mr_data to define the MR transaction.
3. In a separate APB transaction, write the MRCTRL0.mr_wr to 1. This bit is self-clearing, and triggers the MR transaction. The UDDRC then asserts the MRSTAT.mr_wr_busy while it performs the MR transaction to SDRAM, and no further accesses can be initiated until it is deasserted.