17.5.4 Address Collision Handling
The UDDRC can execute transactions out-of-order while ensuring that all transactions appear as if they are executed in the order in which they are received. Every transaction that requires a response from the UDDRC arrives with a token number which is provided back to the SoC core as part of the response. Since the UDDRC queues transactions prior to execution, it is possible that multiple transactions to the same SDRAM address arrive before the first transaction to that address is issued.
For address collision, two HIF addresses are considered the same address if all of the
HIF address bits (except for the LSB column values) are the same. That is, the
“collision” ignores the LSB column values when comparing addresses. The following HIF
address bits are ignored during comparison:
- HIF[2+addrmap_col_b2]
- HIF[1:0]