17.5.6 Bypass Operation

The bypass engine in the UDDRC handles high-priority, low-latency read requests.

The UDDRC supports two priority levels for read commands – high priority reads (HPR) and low priority reads (LPR). The Read CAM can be split into low and high priority sections using the SCHED.lpr_num_entries register. Generally, all the read commands of the controller are stored in the Read CAM. HPR commands are directed to the HP section and LPR commands directed to the LP section. The commands are then scheduled based on several factors such as priority, page match, and oldest entry. The HPR commands in the CAM are given higher priority over the LPR commands by the scheduling engine. However, the HPR commands can be present in the CAM for longer duration due to several factors.

If the bypass operation is enabled, the HPR commands can bypass the CAM and go directly to the PHY interface engine, thereby saving several clocks in latency.

The bypass and the CAM paths are shown in the following figure.

Figure 17-4. Bypass and CAM Paths

There are two types of bypass operations:

  • Activate Bypass operation: if a HP Read command comes to a closed page, then the Activate request for this command is sent through the Bypass path. The command is still sent to the CAM and the Read part of this request happens through the CAM scheduling logic.
  • Read Bypass operation: if a HP Read command comes to a page that is already open, then the Activate request is not necessary for this command. The Read is sent through the Bypass path.

Even if the input command satisfies the above mentioned conditions for the bypass operation, the command may not go through the Bypass path.

There are several reasons for this:

  • The Controller is in Write mode.
  • The Controller is performing critical maintenance commands such as Refresh, ZQ Calibration, MRW/MRR, and Critical Pre-charge.
  • The Controller is handling a collision scenario.
  • The Controller is performing a DFI Control Update request.

The idle latency through the DDRC for an Activate or a Read command going through the CAM path is 4 cycles. The idle latency when the same command goes through the Bypass path is 2 cycles.