17.5.10 ODT Control

By default, ODT to memories is driven to all zeros.

The register inputs control the following:

  • ODTMAP.rank*_wr_odt: the value desired for ODT following a write command (see Register Descriptions).
  • ODTCFG.wr_odt_delay: the number of cycles to delay following a write command before driving the programmed values for write ODT, which depends primarily on CAS latency.
  • ODTCFG.wr_odt_hold: the number of cycles to hold the programmed write value after it is first driven.
  • ODTMAP.rank*_rd_odt: the value desired for ODT following a read command.
  • ODTCFG.rd_odt_delay: the number of cycles to delay following a read command before driving the programmed values for write ODT, which depends primarily on CAS latency.
  • ODTCFG.rd_odt_hold: the number of cycles to hold the programmed read value after it is first driven.
Note:
  1. ODT control for memories is not required for LPDDR2. It is a DDR2/DDR3/LPDDR3 specific feature.
  2. For LPDDR2, set ODTMAP.rank*_wr/rd_odt to all zeroes.

All of these must be set by the SoC core before taking the UDDRC out of reset. They are then applied to every read or write issued by the UDDRC.

For recommended settings for ODT-related registers in each protocol, see Register Descriptions.