47.7.3 SPDIF Receiver Interrupt Enable Register

This register can only be written if the WPITEN bit is cleared in the SPDIF Receiver Write Protection Mode Register.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Enables the corresponding interrupt.

Name:	SPDIFRX_IER
Offset:	0x10
Reset:	–
Property:	Write-only


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
		CP_ERR	PRE_ERR	NRZ_ERR	BLOCKST	SECE	C2SC	C1SC
Access		W	W	W	W	W	W	W
Reset		–	–	–	–	–	–	–


Bit	7	6	5	4	3	2	1	0
	RXFULL	OVERRUN	PAR_ERR	SFE	BLOCKEND	LOSS	LOCKED	RXRDY
Access	W	W	W	W	W	W	W	W
Reset	–	–	–	–	–	–	–	–

Bit 14 – CP_ERR 16 Consecutive Preamble Errors Interrupt Enable

Bit 13 – PRE_ERR Preamble Error (Code Violation) Enable

Bit 12 – NRZ_ERR NRZ Biphase Mark Error in Payload Data (Code Violation) Enable

Bit 11 – BLOCKST Start of Block Interrupt Enable

Bit 10 – SECE Security Report Interrupt Enable

Bit 9 – C2SC Bit 0 to 31 Channel 2 Status Change Interrupt Enable

Bit 8 – C1SC Bit 0 to 31 Channel 1 Status Change Interrupt Enable

Bit 7 – RXFULL Receiver FIFO Full Interrupt Enable

Bit 6 – OVERRUN FIFO Overrun, Interrupt Enable

Bit 5 – PAR_ERR Parity Bit Error Interrupt Enable

Bit 4 – SFE Sampling Frequency Change Event Interrupt Enable

Bit 3 – BLOCKEND End of Block Interrupt Enable

Bit 2 – LOSS Loss of Signal Activity While Locked Interrupt Enable

Bit 1 – LOCKED Receiver Synchronized Interrupt Enable

Bit 0 – RXRDY Receive Data Ready Interrupt Enable

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.