47.7.7 SPDIF Receiver Status Register

Note: This status register is not cleared on read; it reports the current state of the receiver.
Name: SPDIFRX_RSR
Offset: 0x20
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
     IFS[11:8] 
Access RRRR 
Reset 0000 
Bit 2322212019181716 
 IFS[7:0] 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
     NOSIGNALLOWFBADFULOCK 
Access RRRR 
Reset 0000 

Bits 27:16 – IFS[11:0] Image of Sampling Frequency

When ULOCK=0, IFS returns the number of GCLK periods for two symbols. This field can be used to approximate the sample frequency (fS).

f S (kHz) ≈ f GCLK (kHz) 32 × IFS

with IFS in decimal.

Bit 3 – NOSIGNAL No Signal on Receive Line

ValueDescription
0 The receiver is synchronized or searching for receive line frequency or preambles.
1 The receiver is not able to find any activity (no edge) on RX line.

Bit 2 – LOWF Low Clock Frequency Provided on GCLK Clock

ValueDescription
0 The receiver is synchronized or the receiver is determining the sample frequency of the receive line or searching preambles.
1 The receiver is not able to recover the protocol because the GCLK clock frequency is lower than the minimum required.

Bit 1 – BADF Bad Format Detected on SPDIF RX Line

ValueDescription
0 The receiver is synchronized or the receiver is searching for SPDIF receive line frequency or preambles.
1 The receiver is not able to detect a SPDIF format on the receive line.

Bit 0 – ULOCK Unlocked Receiver

ValueDescription
0 The receiver is synchronized and loads data, or the receiver is disabled.
1 The receiver is not locked because it is searching for SPDIF receive line frequency or preambles. See BADF, LOWF, and NOSIGNAL for reasons of unlocked state.