47.7.4 SPDIF Receiver Interrupt Disable Register
This register can only be written if the WPITEN bit is cleared in the SPDIF Receiver Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
| Name: | SPDIFRX_IDR |
| Offset: | 0x14 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | CP_ERR | PRE_ERR | NRZ_ERR | BLOCKST | SECE | C2SC | C1SC | |
| Access | | W | W | W | W | W | W | W | |
| Reset | | – | – | – | – | – | – | – | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | RXFULL | OVERRUN | PAR_ERR | SFE | BLOCKEND | LOSS | LOCKED | RXRDY | |
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
Bit 14 – CP_ERR 16 Consecutive Preamble Errors Interrupt
Enable
Bit 13 – PRE_ERR Preamble Error (Code
Violation) Disable
Bit 12 – NRZ_ERR NRZ Biphase Mark
Error in Payload Data (Code Violation) Disable
Bit 11 – BLOCKST Start of Block
Interrupt Disable
Bit 10 – SECE Security Report Interrupt Disable
Bit 9 – C2SC Bit 0 to 31 Channel 2 Status Change Interrupt Disable
Bit 8 – C1SC Bit 0 to 31 Channel 1 Status Change Interrupt Disable
Bit 7 – RXFULL Receiver FIFO Full Interrupt
Disable
Bit 6 – OVERRUN FIFO Overrun, Interrupt
Disable
Bit 5 – PAR_ERR Parity Bit Error Interrupt
Disable
Bit 4 – SFE Sampling Frequency Change Event Interrupt
Disable
Bit 3 – BLOCKEND End of Block Interrupt Disable
Bit 2 – LOSS Loss of Signal Activity While Locked Interrupt
Disable
Bit 1 – LOCKED Receiver Synchronized Interrupt Disable
Bit 0 – RXRDY Receive Data Ready Interrupt Disable
