74.6.6.1.2 FLEXCOM SPI Timings
The timings shown in the table below are provided in the following
domains:
- 1.8V domain: VDDIO from 1.7V to 1.9V, maximum external capacitor = 10 pF, DRV = 1, SR = 1
- 3.3V domain: VDDIO from 3.0V to 3.6V, maximum external capacitor = 10 pF, DRV = 0, SR = 1
Symbol | Parameter | Min | Max | Unit |
---|---|---|---|---|
Host Mode | ||||
fSPCK | Frequency in Host mode | – | 40 | MHz |
SPI0 | MISO input setup time before SPCK rises | 20 | – | ns |
SPI1 | MISO input hold time after SPCK rises | 0 | – | ns |
SPI2 | SPCK rising to MOSI delay | 0 | 10 | ns |
SPI3 | MISO input setup time before SPCK falls | 20 | – | ns |
SPI4 | MISO input hold time after SPCK falls | 0 | – | ns |
SPI5 | SPCK falling to MOSI delay | 0 | 10 | ns |
Client Mode | ||||
fSPCK | Frequency in Client mode | – | 20 | MHz |
SPI6 | SPCK falling to MISO delay | 4 | 20 | ns |
SPI7 | MOSI input setup time before SPCK rises | 3 | – | ns |
SPI8 | MOSI input hold time after SPCK rises | 3 | – | ns |
SPI9 | SPCK rising to MISO delay | 4 | 20 | ns |
SPI10 | MOSI input setup time before SPCK falls | 3 | – | ns |
SPI11 | MOSI input hold time after SPCK falls | 3 | – | ns |
SPI12 | CS low before SPCK rising | 6 | – | ns |
SPI13 | SPCK falling to CS high | – | 1 | ns |
SPI14 | CS low before SPCK falling | 6 | – | ns |
SPI15 | SPCK falling to CS high | – | 1 | ns |
SPI16 | NPCS falling to MISO valid | 20 | – | ns |