64.6.10.6.1 Memory Registers/Commands Access

To perform memory register/command accesses, QSPI_IFR.TFRTYP must be set to 0.

If the frame does not contain any data (such as the WRITE ENABLE command) or if QSPI_IFR.SMRM is set to 1, the user must first configure the address to send by writing ADDR in the Instruction Address register (QSPI_IAR) (if the frame contains an address field).

• SMRM=1

  When QSPI_IFR.SMRM is set to 1, accesses to the memory are triggered and controlled by QSPI registers.

  QSPI_IAR.ADDR must be configured if the frame contains an address field.

  QSPI_IFR.APBTFRTYP defines whether the access is a read or a write access. Write frames are triggered by writing QSPI_TDR, and read frames (or frames with no data such as WRITE_ENABLE) are triggered by setting QSPI_CR.STTFR. Each time a new transfer is issued, an SPI transfer is performed with a byte size or halfword size if the QSPI_IFR.WIDTH field is configured to either OCT_OUTPUT, OCT_IO or OCT_CMD and QSPI_IFR.DDREN=1. Reading QSPI_RDR triggers a new read access to the next sequential data in the memory. QSPI_TDR can be written when the flag TDRE is set. The QSPI transfer ends by writing QSPI_CR.LASTXFER. See Figure 64-13 for details.

• SMRM=0

  When QSPI_IFR.SMRM is set to 0, accesses to the memory are triggered by performing an access in the QSPI memory space. The address of the instruction frame is defined by the address of the first data access in the QSPI memory space. The addresses of the next accesses are not used by the QSPI.