22.3.1.2 Clock and SCD Frequency

The BiSS clock is generated from the clock source selected using CLKSEL bits. Use the CLKDIV register bits to divide this clock further. It is the user's responsibility to select the appropriate value of CLKDIV to generate a 20 MHz protocol clock based on BiSS clock selection.

After the clock division, the clock is fed through the SFREQ divider and becomes the clock at which Single Cycle Data will be transmitted.