22 Register Summary


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x1F00	B1SCDATA0L	31:24	SCDATA0L[31:24]
		23:16	SCDATA0L[23:16]
		15:8	SCDATA0L[15:8]
		7:0	SCDATA0L[7:0]
0x1F04	B1SCDATA0H	31:24	SCDATA0H[31:24]
		23:16	SCDATA0H[23:16]
		15:8	SCDATA0H[15:8]
		7:0	SCDATA0H[7:0]
0x1F08	B1SCDATA1L	31:24	SCDATA1L[31:24]
		23:16	SCDATA1L[23:16]
		15:8	SCDATA1L[15:8]
		7:0	SCDATA1L[7:0]
0x1F0C	B1SCDATA1H	31:24	SCDATA1H[31:24]
		23:16	SCDATA1H[23:16]
		15:8	SCDATA1H[15:8]
		7:0	SCDATA1H[7:0]
0x1F10	B1SCDATA2L	31:24	SCDATA2L[31:24]
		23:16	SCDATA2L[23:16]
		15:8	SCDATA2L[15:8]
		7:0	SCDATA2L[7:0]
0x1F14	B1SCDATA2H	31:24	SCDATA2H[31:24]
		23:16	SCDATA2H[23:16]
		15:8	SCDATA2H[15:8]
		7:0	SCDATA2H[7:0]
0x1F18	B1SCDATA3L	31:24	SCDATA3L[31:24]
		23:16	SCDATA3L[23:16]
		15:8	SCDATA3L[15:8]
		7:0	SCDATA3L[7:0]
0x1F1C	B1SCDATA3H	31:24	SCDATA3H[31:24]
		23:16	SCDATA3H[23:16]
		15:8	SCDATA3H[15:8]
		7:0	SCDATA3H[7:0]
0x1F20 ... 0x1F7F	Reserved
0x1F80	B1RDATA0	31:24	RDATAy[23:16]
		23:16	RDATAy[15:8]
		15:8	RDATAy[7:0]
		7:0	RDATAy/IDS0[7:0]
0x1F84	B1RDATA1	31:24	RDATAy[23:16]
		23:16	RDATAy[15:8]
		15:8	RDATAy[7:0]
		7:0	RDATAy/IDS1[7:0]
0x1F88	B1RDATA2	31:24	RDATAy[23:16]
		23:16	RDATAy[15:8]
		15:8	RDATAy[7:0]
		7:0	RDATAy/IDS2[7:0]
0x1F8C	B1RDATA3	31:24	RDATAy[23:16]
		23:16	RDATAy[15:8]
		15:8	RDATAy[7:0]
		7:0	RDATAy/IDS3[7:0]
0x1F90	B1RDATA4	31:24	RDATAy[23:16]
		23:16	RDATAy[15:8]
		15:8	RDATAy[7:0]
		7:0	RDATAy/IDS4[7:0]
0x1F94	B1RDATA5	31:24	RDATAy[23:16]
		23:16	RDATAy[15:8]
		15:8	RDATAy[7:0]
		7:0	RDATAy/IDS5[7:0]
0x1F98	B1RDATA6	31:24	RDATAy[23:16]
		23:16	RDATAy[15:8]
		15:8	RDATAy[7:0]
		7:0	RDATAy/IDS6[7:0]
0x1F9C	B1RDATA7	31:24	RDATAy[23:16]
		23:16	RDATAy[15:8]
		15:8	RDATAy[7:0]
		7:0	RDATAy/IDS7[7:0]
0x1FA0 ... 0x1FBF	Reserved
0x1FC0	B1CLTCON0	31:24	CRCSEED0[15:8]
		23:16	CRCSEED0[7:0]
		15:8	CRCSEL0	CRCLEN0[6:0]/CRCPOLY0[6:0]
		7:0	GRAY0/LSTOP0	SCDEN0	SCDLEN0[5:0]
0x1FC4	B1CLTCON1	31:24	CRCSEED1[15:8]
		23:16	CRCSEED1[7:0]
		15:8	CRCSEL1	CRCLEN1[6:0]/CRCPOLY1[6:0]
		7:0	GRAY1/LSTOP1	SCDEN1	SCDLEN1[5:0]
0x1FC8	B1CLTCON2	31:24	CRCSEED2[15:8]
		23:16	CRCSEED2[7:0]
		15:8	CRCSEL2	CRCLEN2[6:0]/CRCPOLY2[6:0]
		7:0	GRAY2/LSTOP2	SCDEN2	SCDLEN2[5:0]
0x1FCC	B1CLTCON3	31:24	CRCSEED3[15:8]
		23:16	CRCSEED3[7:0]
		15:8	CRCSEL3	CRCLEN3[6:0]/CRCPOLY3[6:0]
		7:0	GRAY3/LSTOP3	SCDEN3	SCDLEN3[5:0]
0x1FD0 ... 0x1FDF	Reserved
0x1FE0	B1RCCON	31:24			REGNUM[5:0]
		23:16	WNR	STRTADDR[6:0]
		15:8
		7:0
0x1FE4	B1CTRLCON	31:24							NOCRC	BANKSWEN
		23:16	Reserved[2:0]			SFREQ[4:0]
		15:8	CTS	PROTOSEL	IDADISCLNTID0[2:0]				MOEN	HOLDCDM
		7:0	CHSEL[7:0]
0x1FE8	B1CCON	31:24
		23:16
		15:8	MODELAY[7:0]
		7:0	FREQAGS[7:0]
0x1FEC	B1CHCON	31:24	ACTSEN[7:0]
		23:16	CLCHCFG7[1:0]		CLCHCFG6[1:0]		CLCHCFG5[1:0]		CLCHCFG4[1:0]
		15:8	CLCHCFG3[1:0]		CLCHCFG2[1:0]		CLCHCFG1[1:0]		CLCHCFG0[1:0]
		7:0	CLNTLOC[7:2]							CLNTLOC1
0x1FF0	B1STAT	31:24	CDMTO	CDSSEL	REGBYTESV[5:0]
		23:16
		15:8	CLSCDV3		CLSCDV2		CLSCDV1		CLSCDV0
		7:0	ERR	AGSERR	DLYERR	SCDTXERR	REGERR		REGEND	EOT
0x1FF4	B1INSTR	31:24
		23:16
		15:8	Reserved[3:0]
		7:0	BREAK	BNKLOCK	SWBANK	INIT	INSTR[2:0]			AGS
0x1FF8	B1CHSTAT	31:24								BKSWERR
		23:16
		15:8	CDS7	SL7	CDS6	SL6	CDS5	SL5	CDS4	SL4
		7:0	CDS3	SL3	CDS2	SL2	CDS1	SL1	CDS0
0x1FFC	B1CON	31:24	INSTRWA	INSTRWE	REGAE			TXRDEN	SCDRST	REGRST
		23:16	CLKDIV[7:0]
		15:8	ON		SLPEN	SIDL	CDM	CDS	SENSESEL	GETSENSE
		7:0	DISSI	DISMA	DISSO	REGACC	BNKNUM	ACTIVE		CLKSEL