15.4.9 Test Mode

The test mode allows the ADC controller to be tested. This mode is enabled when the TSTEN bit (ADnCON[8]) is set. When enabled, the result of any conversion is overwritten with a value from the ADnDATAOVR register. The TSTEN bit can be protected from an unintentional write by setting of the TSTLOCK bit (ADnCON[10]) .

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