15.4.4 Conversions

Each channel can be triggered to do a single conversion or accumulate results of the multiple conversions. The conversion mode is selected by MODE[1:0] bits (ADnCHCONx[31:30]). Depending on the conversion mode, the channel conversions are initiated by triggers defined in TRG1SRC[4:0] and TRG2SRC[4:0] bits (ADnCHxCON[4:0] and ADnCHxCON[23:19]).

The following conversion modes are available:

• Single conversion (MODE[1:0] bits = ‘00’). The conversion is initiated by TRG1SRC[4:0] trigger. When the conversion is finished the conversion result is stored in the ADnCHxDATA register, the CHxRDY bit in the ADnSTAT register is set and the ADnCHxIF interrupt flag in the corresponding IFCx register is set.
• Window conversions (MODE[1:0] bits = ‘01’). In this mode, the conversion results are accumulated in the ADnCHxDATA register (primary accumulator) when a signal selected by the TRG1SRC[4:0] bits has an active level. The active level can be changed by the TRG1POL bit (ADnCHxCON[25]). All conversions are initiated by a trigger selected in the TRG2SRC[4:0] bits (ADnCHxCON[23:19]). The number of conversions is limited by the CNTx[15:0] bits (ADnCNTx[15:0]). The number of accumulated conversion results is available in the CNTSTATx[15:0] bits (ADnCHxCNT[31:16]). CHxRDY bit in the ADnSTAT register and the ADnCHxIF interrupt flag in the corresponding IFCx register are set when the gating signal selected by the TRG1SRC[4:0] bits is deactivated or when the number of accumulated conversion results reaches a limit defined by the CNTx[15:0] bits.
• Integration (MODE[1:0] bits = ‘10’). In this mode, the number of conversion results defined by the CNTx[15:0] bits (ADnCHxCNT[15:0]) are accumulated in the ADnCHxDATA register (primary accumulator). The first conversion is initiated by a trigger selected by the TRG1SRC[4:0] bits and all other conversions are executed by a trigger selected by TRG2SRC[4:0] bits. When the number of accumulated conversion results reaches a value in the CNTx[15:0] bits (ADnCHxCNT[15:0]), the CHxRDY bit in ADnSTAT register and the ADnCHxIF interrupt flag in the corresponding IFCx register are set.
• Oversampling (MODE[1:0] bits = ’11’). In this mode, the number of conversion results defined by the ACCNUM[1:0] bits (ADnCHxCON[21:20]) are accumulated in the ADnCHxDATA register (primary accumulator). The first conversion is initiated by a trigger selected by the TRG1SRC[4:0] bits and all other conversions are executed by a trigger selected by TRG2SRC[4:0] bits. When the number of the accumulated conversion results reaches a value specified in the ACCNUM[21:20] bits, the CHxRDY bit in the ADnSTAT register and the ADnCHxIF interrupt flag in the corresponding IFCx register are set. The oversampling process can be delayed by high priority channel conversions. The ACCBRST bit (ADnCHxCON[27]) can disable the interruption by other high priority channels. When the ACCBURST bit is set (’1’), all other conversions will be suspended until all oversampling conversions for this channel are finished.