24.4.6.2.1 Retrigger Operation

The RTRGEN bit (CCPxCON1[30]) allows the timer to be retriggered while the CCPTRIG bit remains set. When RTRGEN is set, a second trigger event occurring during trigger operation will cause the timer to reset and start counting again. Figure 24-28 shows how the timer restarts counting when the trigger comes again, before the timer overflow happens.

When RTRGEN = 1, multiple trigger pulses occurring within the same time base clock period will not be recognized and will be treated as a single trigger event. If trigger pulses are received on two adjacent timer clock periods, the time base will be held in Reset (0000h) for one additional clock period.