24.5.3.1 Interrupt Configuration

The CCPx module has a dedicated Interrupt flag bit (CCT/PxIF) and a corresponding Interrupt Enable/Mask bit (CCT/PxIE).

The CCT/PxIE bit is used to define the behavior of the interrupt controller when the CCT/PxIF bit is set. When the CCT/PxIE bit is clear, the interrupt controller does not generate a CPU interrupt for the event. If the CCT/PxIE bit is set, the interrupt controller generates an interrupt to the CPU when the CCT/PxIF bit is set (subject to the interrupt priority).

The software routine that services a particular interrupt must clear the appropriate Interrupt Flag bit before the service routine is complete. The priority of the CCPx module can be set with the CCT/PxIP[2:0] bits. This priority defines the priority group to which the interrupt source will be assigned. The priority groups range from a value of seven (the highest priority) to a value of 0 (which does not generate an interrupt). An interrupt being serviced will be preempted by an interrupt in a higher priority group.

After an enabled interrupt is generated, the CPU will jump to the vector assigned to that interrupt. The vector number for the interrupt is the same as the natural order number. The CPU will then begin executing code at the vector address. Code at this vector address should perform any application-specific operations and clear the CCT/Px1IF interrupt flag and then exit.