24.5.3 Interrupts

The CCP module has the ability to generate the interrupt on the period match input capture event or output compare event. The CCP module is enabled as a source of interrupt via the CCP Interrupt Enable bit, CCTxIE and CCPxIE. The CCP Interrupt Priority Level is defined by the CCP Interrupt Priority bits CCTxIP[2:0] and CCPxIP[2:0].

CCTxIF is set when the TMRx count matches the respective PRx register. CCPxIF is set whenever there is an input capture event or an output compare equal event. The CCTxIF and CCPxIF bits must be cleared in software.