22.2.5.1.1 Clock Frequency Generation

The BiSS module supports multiple clock sources that can be selected using CLKSEL register bits. After the clock source is selected, the first clock divider can be set up by setting the CLKDIV register. The BiSS module is expected to receive a maximum of 20 MHz CLK from the CLKDIV block. Select the CLKDIV value so that the CLK value is not more than 20 MHz. Setting the SFREQ register configures the SCD frequency (MA Clock). With a module divided clock frequency of 20 MHz, the clock frequency at MA ranges from 10 MHz down to 62.5 kHz.