31.3.4.2 Clearing Post-DMT Event

The DMT NMI will cause the processor to execute a trap handler (ISR) that will decide what to do. The user may decide to reset the DMT through the Post-Clearing (PPPC followed by PPC) mechanism, or the user can execute a RESET instruction to reset the system in the trap handler.

Clearing the DMT counter post-expiry requires a special sequence of operations:

  1. The NMI_STEP1[7:0] bits in the PPPC register must be written as ‘01000000b’.
  2. The NMI_STEP2[7:0] bits in the PPC register must be written as ‘10001000b’. This can only be done if preceded by NMI_STEP1.

If any value other than ‘01000000b’ is written to the NMI_STEP1 bits, this register remains unchanged and the instruction writing to it is considered to be unsuccessful. Any value other than ‘10001000b’ written to the NMI_STEP2 bits renders the operation unsuccessful.

Figure 31-3. Flowchart for Clearing Post-DMT Event