23.4.6.3 Prescaler with External Clock

In all modes, the prescaler enable signal is generated based on the System Clock domain TCS and TGATE bit settings; therefore, these bits should not be modified while the timer is enabled to avoid clock domain crossing issues (refer to Figure 23-9).

Figure 23-9. Asynchronous Prescale External Clock Mode Timing Diagram

When a synchronized clock is chosen, whether the source is internal or external, the prescaler Reset logic will use the System Clock. The prescaler Reset signal is generated by writes to TMRx using System Clock.

When an asynchronous clock is chosen, the prescaler Reset logic will be generated from the external clock asynchronous domain. The prescaler Reset event will be generated by the timer write event, which is synchronous to the external clock domain.