2.4 Transmit Buffer

The stand-alone I²C module has a dedicated transmit buffer, I2CxTXB, which operates independently from the receive buffer.

The transmit buffer is loaded with an address or data byte that is to be shifted into the transmit shift register and transmitted onto the bus. When the I2CxTXB is empty, the Transmit Buffer Empty Status (TXBE) bit is set, allowing user software or the DMA to load another byte into the buffer. Once the data is transmitted from the I2CxTXB register, the TXBE bit is cleared. If user software attempts to load the I2CxTXB while it is full (TXBF = 1), the Transmit Write Error Status (TXWE) bit is set, a NACK is generated, and the new data is ignored. If the TXWE Flag is set, software must clear this bit before attempting to load the buffer again. Additionally, setting the Clear Buffer (CLRBF) bit clears both the transmit and receive buffers, as well as the I2C Transmit Interrupt Flag (I2CxTXIF) bit and I2C Receive Interrupt Flag (I2CxRXIF) bit.