2.10 Bus Time-Out
SMBus and PMBus protocols require a bus watchdog to prevent a stalled device from hanging the bus indefinitely. The I2C module provides a bus time-out feature that can be used to reset the module if one of the bus devices is taking too long to respond. The I2C Bus Time-Out (I2CxBTO) register is used to select the time-out source for the module. When the time-out source expires, the I2CxBTO register notifies the module hardware and resets the module.
If the module is configured as a slave and a bus time-out event occurs while
the slave is active (Slave Mode Active bit (SMA) = 1), the SMA and
Slave Clock Stretching (CSTR) bits are cleared, the module is reset, and the Bus
Time-Out Interrupt Flag (BTOIF) bit is set.
If the module is configured as a master and a bus time-out event occurs
while the master is active (Master Mode Active bit (MMA) = 1), the
module immediately attempts to transmit a Stop condition and sets BTOIF. Generation of
the Stop condition may be delayed if a slave is stretching the clock. The MMA bit is
only cleared after a Stop condition has been generated (see figure below).
