2.7 Acknowledge (ACK)/Not Acknowledge (NACK) Sequence

The I²C specification defines the Acknowledge sequence as a logic low state of the SDA line during the 9th SCL pulse for any successfully transferred byte. During this time, the transmitter must relinquish control of the SDA line to the receiver. The receiver must then pull the SDA line low and keep it low during the high period of the 9th SCL pulse.

When the receiver has successfully received a matching address byte or a valid data byte, it will pull the SDA line low during the 9th SCL pulse, which indicates to the transmitter that is has successfully received the information and is ready for the next byte.

An Acknowledge sequence is enabled automatically by hardware following an address/data byte reception. On the 8th falling edge of SCL, the contents of either the Acknowledge Data (ACKDT) bit or the Acknowledge End of Count (ACKCNT) bit is copied to the SDA output. When I2CxCNT is not ‘0’, the value of the ACKDT bit is copied to SDA. When I2CxCNT is ‘0’, the value of the ACKCNT bit is copied to SDA. In most applications, the value of ACKDT may be ‘0’, which represents an ACK (see figure below).

If the SDA line remains at a high logic level during the 9th SCL pulse, this is defined as a Not Acknowledge (NACK) sequence (see figure below).

A NACK is generated when any of the following conditions occurs:

• No slave device is present on the bus that owns the transmitted address
• The receiver is busy and is not ready for communication
• The receiver gets data or commands that it cannot understand
• The receiver cannot receive any more data
• A master-receiver has received the requested data and is ready to terminate transmission
• An I²C Error condition has occurred
• The I2CxCNT register has reached a ‘0’ value and ACKCNT is set (ACKCNT = 1).

The master device can then decide to either generate a Stop condition to terminate the transfer, or issue a Restart condition to hold the bus and begin a new transfer.