2.1 Dedicated Transmit/Receive Buffers

The I²C module has two dedicated data buffers, one for transmission (I2CxTXB) and one for reception (I2CxRXB) - see figure below.

The transmit buffer, I2CxTXB, is loaded from software or from the Direct Memory Access (DMA) module (see Figure 2-2). When transmission begins, data loaded into the I2CxTXB is shifted into the transmit shift register and out onto the bus. The I2CxTXB can be loaded when the Transmit Buffer Empty Status (TXBE) bit of the I2CxSTAT1 register is set (TXBE = 1), indicating that the buffer is empty. When the buffer is empty and the I2CxCNT register is not equal to zero (I2CxCNT != 0), the I2C Transmit Interrupt Flag (I2CxTXIF) bit is set (I2CxTXIF = 0), and the generic I2C Interrupt Flag (I2CxIF) bit is also set if the I2C Transmit Interrupt Enable (I2CxTXIE) bit is set (I2CxTXIE = 1). Loading a new byte of data into the I2CxTXB clears the I2CxTXIF Flag bit. If the buffer is loaded when it is full (TXBE = 0), the Transmit Write Error Status (TXWE) bit is set, and the new data is discarded. If TXWE is set, user software must clear this Error condition to resume normal operation.

The receive buffer, I2CxRXB, receives data from the bus via the receive shift register. I2CxRXB can be read through user software or through the DMA (see Figure 2-2). When a new byte is received into I2CxRXB, the Receive Buffer Full Status (RXBF) bit of the I2CxSTAT1 register and the I2C Receive Interrupt Flag (I2CxRXIF) bit are set, and the generic I2CxIF is also set if the I2C Receive Interrupt Enable (I2CxRXIE) is set. Reading the buffer clears both RXBF and I2CxRXIF. If the buffer is read when it is empty (RXBF = 0), the Receive Read Error Status (RXRE) bit is set, and a Not Acknowledge (NACK) is generated. User software must clear the Error condition to resume normal operation.

Both transmit and receive buffers can be cleared by setting the Clear Buffer (CLRBF) bit of the I2CxSTAT1 register, which also clears both the I2CxTXIF and I2CxRXIF Interrupt flags.