2.8 Stop Condition

The I2C specification defines a Stop condition as the transition of the SDA line from an active state to an idle state while the SCL line is idle. The master will issue a Stop condition when it has completed its transactions and is ready to release control of the bus, or if a bus time-out occurs.

Important: Note that at least one SCL low period must appear before a Stop condition is valid. If the SDA line transitions low and then high again while the SCL line is high, the Stop condition is ignored and a Start/Restart condition will be detected by the receiver (see figure below).
Figure 2-7. Stop Condition
Note:
  1. At least one SCL low time must appear before a stop is valid.
  2. See device data sheet for Stop condition setup times.
  3. See device data sheet for Stop condition hold times.

After the ACK/NACK sequence of the final byte of the transmitted/received I2C packet, hardware pulls the SCL line low for TSCL/2, and then releases SCL. Hardware samples SCL to ensure a logic high level. SDA is then released, and the transition of SDA from low to high while SCL is high causes the Stop Condition Interrupt Flag (PCIF) bit to be set.