2.11 Data Byte Count

The data byte count is the number of bytes in a complete I²C packet. The I2C Byte Count (I2CxCNT) register is used to specify the length, in bytes, of the complete transaction. The value loaded into I2CxCNT will decrement each time a data byte is transmitted or received by the module.

When a byte transfer causes the I2CxCNT register to decrement to ‘0’, the Byte Count Interrupt Flag (CNTIF) bit of the I2CxPIR register is set, and if the Byte Count Interrupt Enable (CNTIE) bit of the I2CxPIE register is set,the general purpose I2C Interrupt Flag (I2CxIF) bit is also set. The I2CxIF is a read-only bit and can only be cleared by clearing all enabled Interrupt Flag bits in the I2CxPIR register.

The I2CxCNT register can be read at any time, but it is recommended that a double read is performed to ensure a valid read.

The I2CxCNT register can be written to, but care is required to prevent register corruption. If the I2CxCNT register is written to during the 8th falling SCL edge during reception, or during the 9th falling SCL edge during transmission, the register value may be corrupted. In Slave mode, I2CxCNT can be safely written to any time the slave is stretching the clock (CSTR = 1), or after a Stop condition has been received. In Master mode, I2CxCNT can be safely written to any time the master state machine is paused (MDR = 1), or when the bus is idle (BFRE = 1). If the I²C packet is longer than 255 bytes, the I2CxCNT value can be updated mid-message to prevent the count from reaching ‘0’; however, the preventative measures listed above must be followed.

The I2CxCNT value can be automatically loaded when the Auto-Load I2C Count Register Enable (ACNT) bit of the I2CxCON2 register is set. When ACNT is set, the data byte following the address byte is loaded into I2CxCNT, and the value of the Acknowledge Data (ACKDT) bit is used for the ACK response.

When in either Slave-Read or Master-Write mode and the I2CxCNT value is not ‘0’, the value of the ACKDT bit is used for the ACK response. When I2CxCNT = 0, the value of the Acknowledge End of Count (ACKCNT) bit is used for the ACK response.

When the module is in Master mode and I2CxCNT = 0 and the Restart Enable (RSEN) bit is clear, the master state machine will automatically generate a Stop condition instead of reading/writing another byte. When I2CxCNT = 0 and RSEN = 1, the master will set the Master Data Ready (MDR) bit, stretch the clock, and wait for the Start bit to be set before sending a Restart condition and the address of the slave it wishes to communicate with.