43.4.18 I2C Bus Data Requirements

Table 43-24. 
Standard Operating Conditions (unless otherwise stated)
Param. No. Sym. Characteristic Min. Max. Units Conditions
SP100* THIGH Clock high time 100 kHz mode 4000 — ns Device must operate at a minimum of 1.5 MHz
400 kHz mode 600 — ns Device must operate at a minimum of 10 MHz
SP101* TLOW Clock low time 100 kHz mode 4700 — ns Device must operate at a minimum of 1.5 MHz
400 kHz mode 1300 — ns Device must operate at a minimum of 10 MHz
SP102* TR SDA and SCL rise time 100 kHz mode — 1000 ns
400 kHz mode 20 300 ns CB is specified to be from 10-400 pF
SP103* TF SDA and SCL fall time 100 kHz mode — 250 ns
400 kHz mode 20 × (VDD/5.5V) 250 ns CB is specified to be from 10-400 pF
SP106* THD:DAT Data input hold time 100 kHz mode 0 — ns
400 kHz mode 0 — ns
SP107* TSU:DAT Data input setup time 100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
SP109* TAA Output valid from clock 100 kHz mode — 3450 ns (Note 1)
400 kHz mode — 900 ns
SP110* TBUF Bus free time 100 kHz mode 4700 — ns Time the bus must be free before a new transmission can start
400 kHz mode 1300 — ns
SP111 CB Bus capacitive loading 100 kHz mode — 400 pF
400 kHz mode — 400 pF

* These parameters are characterized but not tested.

Note:
  1. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
  2. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released.
  3. Using internal I2C pull-ups. For greater bus capacitance use external pull-ups.
Figure 43-20. I2C Bus Data Timing
Note: Refer to Figure 43-3 for load conditions.